1. Field of the Invention
The present invention relates to a method for integrating three bipolar transistors into a semiconductor body, a multilayer component, and a semiconductor arrangement.
2. Description of the Background Art
From the document EP 0 493 854, which corresponds to U.S. Pat. No. 5,376,821, and which is hereinafter referred to as D1, are known vertical integrated cascode structures having only two transistors for high voltage applications. In this arrangement, a transistor that has a high blocking capability and is geometrically on the bottom is vertically integrated with a transistor that is geometrically on top. Such arrangements are preferably used in the voltage range above 100 V. The emitter region of the transistor that is geometrically on the bottom has a significantly higher dopant concentration, with the same conductivity type, than an adjacent collector drift zone of the transistor that is geometrically on top. In this way, the emitter efficiency of the transistor that is geometrically on the bottom, in particular, is increased. The vertical integration of two npn transistors, for example, results in a parasitic pnp transistor, so that the arrangement from D1 tends toward thyristor-like behavior and the collector current only remains controllable within limits.
In the document EP 605920, hereinafter referred to as D2, the tendency of the arrangement toward thyristor-like behavior is reduced by increasing the Gummel number GB of the parasitic transistor. To this end, the emitter region of the bottom transistor is implemented as a highly doped layer that thoroughly isolates the base of the bottom transistor from the collector drift zone of the top transistor by creating a mesa structure. In D2, only two transistors can be integrated in the mesa structure. In another embodiment in D2, p-doped SiGe is used as an etch stop for producing the mesa structure in the base of the bottom transistor.